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PLX eNews - October 2009Welcome to PLX's quarterly newsletter and thank you for subscribing. If you can not read this email, please view it on our Website. |
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In this issue:
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Multiple Masters Can Better Serve Next-Generation Designs with PCIe
Read the Article in Computer Tech Review magazine DMA Engines Bring Multicast to PCI Express Systems
Read the Article in Electronic Design magazine Minimizing latency in diverse embedded system design environments
Read the Article on Embedded.com, an EE Times Network Tricks for fixing troublesome PCIe links
Read the Article in Embedded Computing Design magazine PCI Express Gen 3 -- Twice as Nice…
Read the Article in RTC magazine NAS SoCs are the New Generation of Consumer Storage Devices
Read the Article in Digital Home Design Line, an EE Times Network PLX Extends Leadership in USB with New USB 3.0 Solutions for Multiple Markets
Recent PLX USB 3.0 product demonstrations were well-received at leading manufacturers and focused on new performance-leading unique features. The devices also successfully tested and delivered high performance at the SuperSpeed USB Platform Interoperability Lab (PIL). PLX is developing USB 3.0 devices and specialized firmware whose targets also expand into multi-function printers (MFPs), video projectors, ultra-high-speed wireless networking, portable computing, and digital media products.
DAS Storage Controller is Industry's Highest Performance, Lowest Power
PLX Exceeds $100 Million Mark for PCI Express; 16 Million Ports Shipped
PLX PCI Express Gen 2 Switches Support Access Control Service -- Required for I/O Virtualization
All PLX Gen 2 switches also support Alternative Routing-ID Interpretation (ARI), which increases the number of functions a device may support. Additionally, PLX PCIe Gen 2 switches support Multicast (MC), which allows a single ingress packet to be sent to multiple egress ports, delivering significant saving in CPU utilization.
PLX Switch Enables SATA 6Gb/s on ASUS Motherboard
Because Silicon without Software is Just Sand: PCIe SDK 6.3 & Oxide 3.0.1 Available Now
The PCIe SDK v6.3 can be found here ***** *****
Oxide for UARTs can be found here Express APPS - - Quick Review of Ideas for Design
Express App #69 (PDF)
Express App #68 (PDF)
Express App #67 (PDF)
PLX Website Upgrade, New Feature
Technical Support 24/7/365The PLX web-based technical support portal is your ticket to fast relief and problem resolution. We have built a large FAQ site with a broad range of immediate answers. In the event your request can not be found in the current knowledge base, simply enter a new case and our global support team will jump to action. The PLX technical support portal login can be found here http://www.plxtech.com/support/portal. Access datasheets or update your PLX profile and subscriptions by logging in at http://www.plxtech.com/mydata/ |
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To date, most server, embedded and storage systems typically have had a single-master in their hierarchy. One CPU is designated the master and enumerates all the components in the entire system, allocates memory to the end-points and manages most of the transactions -- staying true to its designation of a master. For those applications requiring failover and redundancy, designers needed to use two CPUs, which tend to cause conflict between the two masters. In order to ensure a single-master hierarchy in a PCI Express (PCIe)-based system, those designers used the non-transparent port in a PCIe switch to isolate the two CPUs and remove any conflict between the two masters.
By integrating DMA in a PCIe switch, designers can move large amounts of data from local memory to devices attached to the switch, freeing CPU cycles up for time-critical applications. The internal DMA engine in a PCIe switch can be leveraged and used to perform the multicast function in applications that use small PCIe switches. The advantages for implementing a DMA-based multicast scheme are many: support for an unlimited number of multicast groups (each descriptor ring represents one such group); a reliable multicast scheme (status for each copy made can be provided by the DMA engine); multicast transfers that aren't limited to posted transactions; and most importantly, DMA-based multicast provides a PCIe multicast solution now.
This article will address how latency issues in embedded (and other) systems have been successfully and measurably countered in PCIe's first two generations and what designers can expect with PCIe Gen 3 on the horizon. "High performance" in many instances is associated with high throughput. Though bandwidth and performance go hand in hand, there are other factors that make a significant contribution to system performance where high throughput is not part of the system application. In such applications, latency -- specifically device latency -- plays a larger role in the overall performance.
Designers can take several steps to debug a PCIe channel that shows no signs of linking. PCI Express (PCIe) is a ubiquitous interface for embedded systems, offering several key advantages including auto-detection, lane configurability, robust error detection and correction, high lane-to-lane skew tolerance, and low power. Despite the interface's power and versatility, designers occasionally need to debug a faulty PCIe link.
With each successive generation of the industry standard PCI Express (PCIe) interconnect, the technology has been able to double its bandwidth, while at the same time adding features to improve system robustness. Designers now using PCIe Gen 1 and Gen 2 technology can look forward to another significant performance jump—to an incredibly fast eight gigabits per second (Gbits/s) per lane and 128 Gbit/s in designs using x16 port widths—along with a number of optimizations for enhanced signaling and data integrity, while maintaining full compatibility with the PCIe protocol stack and interoperability with components that support only the lower speed.
The grand vision of accessing content anytime, anywhere, and from any device is becoming more of a reality with this new generation of home storage devices. Now, all digital content from any device can be stored, managed and securely and reliability accessed both within and from outside of the home. Clearly, consumer NAS is taking a more active role in the digital lifestyle by being the conduit for the many diverse features, functions and services that are converging and creating synergy.
PLX announced completion of key design milestones that bring to market diverse USB 3.0 (SuperSpeed USB) solutions for a wide variety of applications. This PLX development expands on the company's USB 2.0 expertise and PCI Express (PCIe) leadership, and will be compliant with the high-performance and interoperability standards of the USB 3.0 specification. PLX USB 3.0 solutions will initially be delivered to designers focused on direct-attached storage (DAS) and network-attached (NAS) external consumer storage products.
Fed up wasting time waiting for backups to complete? Using PLX’s new OXUF943SE bridge to backup up your PC or MAC is up to 70% quicker than the nearest competition. Complete a 100GB backup in only 20 minutes compared to 35 minutes for the nearest competitor! 
PLX reached a new milestone of having shipped more than $100 million in revenue from its industry-leading PLX ExpressLane PCI Express family. PLX, with more than 65 percent of PCIe switch market share, to date has shipped nearly five million switch and bridge units, including 16 million PCIe ports, to board and system designers worldwide. PCI Express has clearly become the definitive high-speed serial link of choice for the widest variety of markets, as evidenced by its rapidly growing usage in applications ranging from control planes and embedded-systems to the mainstream use found in enterprise storage, servers and graphics.
PLX's entire PCIe Gen 2 switch family, ranging from four to 96 lanes, is fully compliant to support Access Control Service (ACS), which is required in PCIe switches in various I/O virtualization (IOV) applications. Virtualization allows multiple operating systems running simultaneously within a single computer to share CPU and I/O resources. ACS capability in PLX PCIe switches prevents silent data corruption and un-intended data transfers between partitions of shared resources in virtual computing environments found in modern data centers. Virtual computing is increasingly being deployed in data centers to reduce capital expenditures and operating expenses.
The PLX PEX 8613 PCIe Gen 2 switch is being used on the new ASUS P7P55D Premium motherboard to support the necessary bandwidth and fan-out required of ASUS's latest high-end innovation. The PLX switch enables the P7P55D Premium to provide powerful system design flexibility by using the PEX 8613 switch to act as a reliable high-performance bridge between the Intel P55 chipset and high-speed Gen 2 I/O endpoints that includes multiple expansion slots and SATA 6Gb/s ports.
Using the PLX PEX 8613 switch as a bridge, P7P55D Premium was able to connect two Gen 2 lanes on the SATA 6Gb/s endpoint to four Gen 1 lanes on the Intel P55 chipset. This flexibility can be found in all PLX PCIe Gen 2 switches, thus allowing designers to take advantage of the newest and highest-performance solutions, while simultaneously accommodating legacy designs.
The PLX PCI Express Software Development Kit (SDK) application offers an easy to use enhanced user interface that includes a variety of new and useful tools that can help in the following ways:
The Oxide SDK supports all PLX Serial Bridges and UARTs. This highly recommended software toolset is fundamental in the design development usage of PLX UARTs and is loaded with practical and intelligent functions including:
Express App #70 (
Engineers can now register to receive alerts whenever a databook, app note or other specification is added or updated. Simply go to any device page to subscribe. You will then receive alerts either by email, or have notes posted on your